Advance Program

Monday, 7/24

7:30

Breakfast (continues until 9:00)

08:00 – 08:40

Conference Registration

08:40 – 09:00

Welcome by General and Program Co-Chairs
[Forum Hall]

09:00 – 10:00

Keynote I

A New Silicon Age 4.0: Generating Semiconductor-Intelligence Paradigm with a Virtual Moore's Law Economics and Heterogeneous Technologies

Dr. Nicky Lu

Etron Technology, Inc.

Chair: Chia-Lin Yang (National Taiwan University)

[Forum Hall]

10:00 – 10:30

Coffee Break

10:30 – 11:45

Session 1A

Memories & their Applications

Session Chair: Sangyoung Park
(TU Műnchen)

[Locke Hall]

Session 1B

Design Implications of Novel Interconnects & Technologies

Session Chair: Alper Buyuktosunoglu
(IBM T.J. Watson Research Center)

[Archimedes Hall]

Write-Energy-Saving ReRAM-Based Nonvolatile SRAM with Redundant Bit-Write-Aware Controller for Last-Level Caches

Tsai-Kan Chien12, Lih-Yih Chiou1, Yi-Sung Tsou1, Shyh-Shyuan Sheu2, Pei-Hua Wang2, Ming-Jinn Tsai2 and Chih-I Wu2

1National Cheng Kung University, 2Industrial Technology Research Institute

Charge Recycled Low Power SRAM with Integrated Write and Read Assist, for Wearable Electronics, Designed in 7nm FINFET Technology

Vivek Nautiyal, Gaurav Singla, Satinderjit Singh, Fakhruddin ali Bohra, Jitendra Dasani, Lalit Gupta and Sagar Dwivedi

ARM, Ltd.

Spin-Torque Sensors with Differential Signaling for Fast and Energy Efficient Global Interconnects

Zubair Azim and Kaushik Roy

Purdue University

A Carbon Nanotube Transistor based RISC-V Processor using Pass Transistor Logic

Best Paper Nominee

Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski and Ron G. Dreslinski

University of Michigan

Architecting Large-Scale SRAM Arrays with Monolithic 3D Integration

Joonho Kong1, Young-Ho Gong2 and Sung Woo Chung2

1Kyungpook National University, 2Korea University

Temporal Codes in On-Chip Interconnects

Michael Mishkin1, Nam Sung Kim2 and Mikko Lipasti1

1University of Wisconsin-Madison, 2University of Illinois Urbana-Champaign

11:45 – 13:00

Lunch
[2F Just Italian, Just Sleep]

13:00 – 14:30

Poster Session

Session Chair: Thomas Wenisch
(University of Michigan)

[Plato Hall]

Design Contest

Session Chairs: Saibal Mukhopadhyay (Georgia Tech), Yongpan Liu (Tsinghua University)

[Plato Hall]

Enabling Efficient Fine-Grained DRAM Activations with Interleaved I/O

Chao Zhang and Xiaochen Guo

Lehigh University

Gabor Filter Assisted Energy Efficient Fast Learning Convolutional Neural Networks

Syed Shakib Sarwar, Priyadarshini Panda and Kaushik Roy

Purdue University

Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology

Sungju Ryu, Jongeun Koo and Jae-Joon Kim

Pohang University of Science and Technology

Efficient Query Processing in Crossbar Memory

Mohsen Imani, Saransh Gupta, Atl Arredondo and Tajana Rosing

UC San Diego

A Low Power Duobinary Voltage Mode Transmitter

Ming-Hung Chien, Yen-Long Lee, Jih-Ren Goh and Soon-Jyh Chang

National Cheng Kung University

A Simple Yet Efficient Accuracy Configurable Adder Design

Wenbin Xu1, Sachin Sapatnekar2 and Jiang Hu1

1Texas A&M University, 2University of Minnesota

E-Spector: Online Energy Inspection for Android Applications

Chengke Wang, Yao Guo, Peng Shen and Xiangqun Chen

Peking University

A Case for Efficient Accelerator Design Space Exploration via Bayesian Optimization

Brandon Reagen1, José Miguel Hernanez-Lobato2, Robert Adolf1, Michael Gelbart3, Paul Whatmough14, Gu-Yeon Wei1 and David Brooks1

1Harvard University, 2University of Cambridge, 3University of British Columbia, 4ARM Research

SceneMan: Bridging Mobile Apps with System Energy Manager via Scenario Notification

Li Li1, Jun Wang2, Xiaorui Wang1, Handong Ye2 and Ziang Hu2

1Ohio State University, 2Huawei Technologies

Online Tuning of Dynamic Power Management for Efficient Execution of Interactive Workloads

James R. B. Bantock, Vasileios Tenentes, Bashir M. Al-Hashimi and Geoff V. Merrett

University of Southhampton

Workload-Driven Frequency-Aware Battery Sizing

Yukai Chen, Enrico Macii and Massimo Poncino

Politecnico di Torino

Exploring Sparsity of Firing Activities and Clock Gating for Energy-Efficient Recurrent Spiking Neural Processors

Yu Liu, Yingyezhe Jin and Peng Li

Texas A&M University

QuARK: Quality-Configurable Approximate STT-MRAM Cache by Fine-Grained Tuning of Reliability-Energy Knobs

Amir Mahdi Hosseini Monazzah1, Majid Shoushtari2, Seyed Ghassem Miremadi1, Amir M. Rahmani23 and Nikil Dutt2

1Sharif University of Technology, 2UC Irvine, 3TU Wien

Efficient Thermoelectric Cooling for Mobile Devices

Youngmoon Lee, Eugene Kim and Kang G. Shin

University of Michigan

Low Power In-Memory Computing based on Dual-Mode SOT-MRAM

Farhana Parveen, Shaahin Angizi, Zhezhi He and Deliang Fan

University of Central Florida

A Low-Power Dual-Core Motion Estimation Chip Design and Implementation for a Wireless Panoramic Endoscopy

Tsung-Yi Wu and Ching-Hwa Cheng

Feng Chia University

An Atomic-Aware Design to Maximize Energy Utilization on NVP-based Self-Powered Sensor Systems

Chih-Kai Kang1, Chun-Han Lin2 and Pi-Cheng Hsiu1

1Academia Sinica, 2National Taiwan Normal University

High Energy-Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Leibo Liu and Shaojun Wei

Tsinghua University

An Ultra-Low Power 169-nA 32.768-kHz Fractional-N PLL

Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu and Tsung-Hsien Lin

National Taiwan University

TeleProbe: Zero-Power Contactless Probing for Implantable Medical Devices

Woo Suk Lee1, Younghyun Kim2 and Vijay Raghunathan3

1Microsoft, 2University of Wisconsin-Madison, 3Purdue University

Retention State-Aware Energy Management for Efficient Nonvolatile Processors

Dongqin Zhou1, Weiwen Chen1, Xin Shi2, Mengying Zhao3 and Keni Qiu14

1Capital Normal University, 2Tsinghua University, 3Shandong University, 4Beijing Advanced Innovation Center for Imaging Technology

1.4-mW, 56-GHz Arithmetic Logic Unit Based on Superconductor Single-Flux-Quantum Logic Circuit

Masamitsu Tanaka1, Ryo Sato1, Yuki Hatanaka1, Yuichiro Matsui1, Hiroyuki Akaike1, Akira Fujimaki1, Koki Ishida2, Takatsugu Ono2 and Koji Inoue2

1Nagoya University, 2Kyushu University

A Reconfigurable Building Block for Thermoelectric Generator Energy Harvesting under Spatial Temperature Variations

Jaemin Kim1, Naehyuck Chang2, Donkyu Baek2, Youngil Kim2 and Donghwa Shin3

1Seoul National University, 2KAIST, 3Yeungnam University

14:30 – 15:45

Session 2A

Analog Circuit Design

Session Chair: Shreyas Sen
(Purdue University)

[Locke Hall]

Session 2B

HW Support for CNNs

Session Chair: Ron Dreslinski
(University of Michigan)

[Archimedes Hall]

A 0.13pJ/bit, Referenceless Transceiver with Clock Edge Modulation for a Wired Intra-BAN Communication

Jihwan Park, Gi-Moon Hong, Mino Kim, Joo-Hyung Chae and Suhwan Kim

Seoul National University

A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter Single Inductor Digital Fractional-n Clock Generator for Reconfigurable Serial I/O

William Y. Li, Hyung Seok Kim, Kailash Chandrashekar, Khoa Nguyen and Ashoke Ravi

Intel Corp.

A Tunable Ultra Low Power Inductorless Low Noise Amplifier Exploiting Body Biasing of 28 nm FDSOI Technology

Jennifer Zaini1, Frédéric Hameau2, Thierry Taris1, Dominique Morche1, Patrick Audebert1 and Eric Mercier1

1CEA Leti, 2University of Bordeaux

CORAL: Coarse-grained Reconfigurable Architecture for Convolutional Neural Networks

Zhe Yuan, Yongpan Liu, Jinshan Yue, Jinyang Li and Huazhong Yang

Tsinghua University

XNOR-POP: A Processing-in-Memory Architecture for Binary Convolutional Neural Networks in Wide-IO2 DRAMs

Lei Jiang1, Minje Kim1, Wujie Wen2 and Danghui Wang3

1Indiana University Bloomington, 2Florida International University, 3Northwestern Polytechnical University

Bit-Width Reduction and Customized Register for Low Cost Convolutional Neural Network Accelerator

Kyungrak Choi, Woong Choi, Kyungho Shin and Jongsun Park

Korea University

15:45 – 16:15

Coffee Break

16:15 – 17:05

Session 3A

Energy Storage & Cyber-Physical Systems

Session Chair: Enrico Macii
(Politecnico di Torini)

[Locke Hall]

Session 3B

Design Methodologies for Machine Learning

Session Chair: Mikko Lipasti
(University of Wisconsin-Madison)

[Archimedes Hall]

Battery Assignment and Scheduling for Drone Delivery Businesses

Best Paper Nominee

Sangyoung Park, Licong Zhang and Samarjit Chakraborty

TU Műnchen

Reconfigurable Thermoelectric Generators for Vehicle Radiators Energy Harvesting

Donkyu Baek1, Caiwen Ding2, Sheng Lin2, Donghwa Shin3, Jaemin Kim4, Xue Lin5, Yanzhi Wang2 and Naehyuck Chang1

1KAIST, 2Syracuse University, 3Yeungnam University, 4Seoul National University, 5Northeastern University

Power Optimizations in MTJ-based Neural Networks through Stochastic Computing

Ankit Mondal and Ankur Srivastava

Universtiy of Maryland

A Learning Bridge from Architectural Synthesis to Physical Design for Exploring Power Efficient High-Performance Adders

Subhendu Roy1, Yuzhe Ma2, Jin Miao1 and Bei Yu2

1Cadence Design Systems, 2Chinese University of Hong Kong

17:30 – 20:00

Industrial Reception (for all registered attendees)
[Living One, National Taiwan University]

Tuesday, 7/25

7:30 – 9:00

Breakfast

09:00 – 10:00

Keynote II

Peering into the Post Moore's Law World

Prof. Todd Austin

University of Michigan

Chair: Thomas Wenisch (University of Michigan)

[Forum Hall]

10:00 – 10:30

Coffee Break

10:30 – 11:45

Session 4A

Low-Voltage & Energy-Efficient Design

Session Chair: Naehyuck Chang
(KAIST)

[Locke Hall]

Session 4B

Approximate & Learn!

Session Chair: Hsiang-Yun Cheng
(Academia Sinica)

[Achimedes Hall]

Comparative Study and Optimization of Synchronous and Asynchronous Comparators at Near-Threshold Voltages

Sung Justin Kim, Doyun Kim and Mingoo Seok

Columbia University

Full Chip Power Benefits with Negative Capacitance FETs

Sandeep K. Samal1, Sourabh Khandelwal2, Asif I. Khan1, Sayeef Salahuddin3, Chenming Hu3 and Sung Kyu Lim1

1Georgia Tech, 2Macquerie University, 3UC Berkeley

Design High Bandwidth-Density, Low Latency and Energy Efficient On-Chip Interconnect

Yong Wang and Hui Wu

University of Rochester

AxSerBus: A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensing

Younghyun Kim1, Setareh Behroozi1, Vijay Raghunathan2 and Anand Raghunathan2

1University of Wisconsin-Madison, 2Purdue University

Approximate Memory Compression for Energy-Efficiency

Ashish Ranjan, Arnab Raha, Vijay Raghunathan and Anand Raghunathan

Purdue University

SENIN: An Energy-Efficient Sparse Neuromorphic System with On-Chip Learning

Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim and Lee-Sup Kim

KAIST

11:45 – 13:15

Lunch
[2F Just Italian, Just Sleep]

13:15 – 14:30

Session 5A

Architecture & Technology Support for Neural Networks

Session Chair: Tsung-Te Liu
(National Taiwan University)

[Locke Hall]

Session 5B

Power Delivery

Session Chair: Pradip Bose
(IBM T. J. Watson Research Center)

[Archimedes Hall]

Monolithic 3D IC Designs for Low-Power Deep Neural Networks Targeting Speech Recognition

Kyungwook Chang1, Deepak Kadetotad2, Yu Cao2, Jae-Sun Seo2 and Sung Kyu Lim1

1Georgia Tech, 2Arizona State University

A Programmable Event-Driven Architecture for Spiking Neural Network Evaluation

Arnab Roy1, Swagath Venkataramani2, Neel Gala1, Sanchari Sen2, Kamakoti Veezhinathan1 and Anand Raghunathan2

1IIT Madras, 2Purdue University

An Energy-Efficient and High-Throughput Bitwise CNN on Sneak-Path-Free Digital ReRAM Crossbar

Leibin Ni1, Zichuan Liu1, Wenhao Song2, J. Joshua Yang2, Hao Yu1, Kenwen Wang3 and Yuangang Wang3

1Nanyang Technological University, 2University of Massachusetts Amherst, 3Huawei Technologies

Placement Mitigation Techniques for Power Grid Electromigration

Wei Ye1, Yibo Lin1, Xiaoqing Xu1, Wuxi Li2, Yiwei Fu2, Yongsheng Sun2, Canhui Zhan2and David Z. Pan1

1UT Austin, 2Hisilicon Technologies

Spatial and Temporal Scheduling of Clock Arrival Times for IR Hot-Spot Mitigation, Reformulation of Peak Current Reduction

Bhoopal Gunna, Lakshmi Bhamidipati, Houman Homayoun and Avesta Sasan

George Mason University

Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs

Kyungwook Chang1, Shidhartha Das2, Saurabh Sinha2, Brian Cline2, Greg Yeric2 and Sung Kyu Lim1

1Georgia Tech, 2ARM

14:30 – 15:00

Coffee Break

15:00 – 16:40

Session 6A

Multi-Scale Energy-Efficient Designs

Session Chair: Yiran Chen
(Duke University)

[Locke Hall]

Session 6B (Special Session)

Interaction of Power Management & Security

Session Chair: TBD

[Archimedes Hall]

ShiftMask: Dynamic OLED Power Shifting Based on Visual Acuity for Interactive Mobile Applications

Han-Yi Lin1, Pi-Cheng Hsiu2 and Tei-Wei Kuo12

1National Taiwan University, 2Academia Sinica

Signal Strength-Aware Adaptive Offloading for Energy Efficient Mobile Devices

Young Geun Kim and Sung Woo Chung

Korea University

Frequency Governors for Cloud Database OLTP Workloads

Rathijit Sen and Alan Halverson

Microsoft

Tiguan: Energy-Aware Collision-Free Control for Large-Scale Connected Vehicles

Minghua Shen and Guojie Luo

Peking University

Ultra-low Energy Security Circuit Primitives for IoT Platforms

Sanu Mathew, Sudhir Satpathy, Vikram Suresh and Ram Krishnamurthy

Intel Labs

Low Power Requirements and Side-Channel Protection of Encryption Engines: Challenges and Opportunities

Monodeep Kar1, Arvind Singh1, Sanu Mathew2, Anand Rajan2, Vivek De2 and Saibal Mukhopadhyay1

1Georgia Tech, 2Intel Labs

Resilient, Energy-Secure Power Management

Pradip Bose and Alper Buyuktosunoglu

IBM T. J. Watson Research Center

Secure Swarm Intelligence: A New Approach to Many-Core Power/Thermal Management

Augusto Vega, Alper Buyuktosunoglu and Pradip Bose

IBM T. J. Watson Research Center

17:30 – 20:30

Banquet
[12F Kunlun Hall, The Grand Hotel]

Wednesday, 7/26

7:30 – 9:00

Breakfast

09:00 – 10:00

Keynote III

Architecture and Software for Emerging Low-Power Systems

Prof. Wen-Mei W. Hwu

University of Illinois Urbana-Champaign

Chair: David Garrett (Broadcom)

[Forum Hall]

10:00 – 10:30

Coffee Break

10:30 – 11:45

Session 7A

Emerging Technologies

Session Chair: David Brooks
(Harvard University)

[Locke Hall]

Session 7B

Low-Power HW Security

Session Chair: Sanu Mathew
(Intel Labs)

[Archimedes Hall]

Transistor-Level Monolithic 3D Standard Cell Layout Optimization for Full-Chip Static Power Integrity

Bon Woong Ku1, Taigon Song2, Arthur Nieuwoudt2 and Sung Kyu Lim1

1Georgia Tech, 2Synopsys

Secure Human-Internet using Dynamic Human Body Communication

Shovan Maity, Debayan Das, Xinyi Jiang and Shreyas Sen

Purdue University

Hotspot Monitoring and Temperature Estimation with Miniature On-Chip Temperature Sensors

Pavan Kumar Chundi, Yini Zhou, Martha Kim, Eren Kursun and Mingoo Seok

Columbia University

A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function

Best Paper Nominee

Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi and Chris H. Kim

University of Minnesota

An Improved Clocking Methodology for Energy Efficient Low Area AES Architectures using Register Renaming

Siva Nishok Dhanuskodi and Daniel Holcomb

University of Massachusetts Amherst

A Low-Power APUF-based Environmental Abnormality Detection Framework

Hongxiang Gu, Teng Xu and Miodrag Potkonjak

UC Los Angeles

11:45 – 12:00

Closing Remarks
[Forum Hall]

12:00 – 12:30

Sack Lunch

12:30 –

Embedded Tutorial

Tiny Light-Harvesting Photovoltaic Charger-Supplies

Gabriel A. Rincón-Mora

Georgia Tech

[Forum Hall]

Excursions

(Optional, tickets can be purchased at the online registration system)