1	"DuraCap: a Supercapacitor-Based, Power-Bootstrapping, Maximum Power Point Tracking Energy-Harvesting System"
4	Small-Area and Low-Energy K-Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding
9	A Practical Low Latency Router Architecture with Wing Channel for On-Chip Network
12	Clock Network Design for Ultra-Low Power Applications
18	Power-Efficient Directional Wireless Communication on Small Form-Factor Mobile Devices
19	Low Power Branch Prediction for Embedded Application Processors
20	A Low-Power Digitally-Programmable Variable Gain Amplifier in 65 nm CMOS
21	SHARP: An Effective Power-Saving Buffer Cache Management Scheme in Heterogeneous Storage Environments
29	TurboTag: Lookup Filtering to Reduce Coherence Directory Power
39	Maximum Power Transfer Tracking for a Photovoltaic-Supercapacitor Energy System
40	Leakage Minimization Using Self Sensing and Thermal Management
42	Analog Circuit Shielding Routing Algorithm Based on Net Classification
43	A 5V Output Voltage Boost Switching Converter with Hybrid Digital and Analog PWM Control
47	Tradeoff between Energy Savings and Privacy Protection in Computation Offloading
63	"A 65nm CMOS Low-Power, Low-Voltage Bandgap Reference with Using Self-biased Composite Cascode Opamp"
66	STM versus Lock-based Systems: An Energy Consumption Perspective
69	MODEST : A Model for Energy Estimation under Spatio-Temporal Variability
72	A New Paradigm in the Design of Energy-Efficient Digital Circuits Using Laterally-Actuated Double-Gate NEMS
75	Rank-Aware Cache Replacement and Write Buffering to Improve DRAM Energy Efficiency
83	NBTI-Aware DVFS: A New Approach to Saving Energy and Increasing Processor Lifetime
89	Workload-Adaptive Process Tuning Strategy for Power-Efficient Multi-Core Processors
96	Energy and Thermal-Aware Video Coding via Encoder/Decoder Workload Balancing
99	"A 6µW, 100Kbps, 3-5GHz, UWB Impulse Radio Transmitter"
101	Low-Power Current-Mode Transceiver for On-chip Bidirectional Buses
102	Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM
103	Distributed DVFS Using Rationally-Related Frequencies and Discrete Voltage Levels
104	0.5-V Operation Variation-Aware Word-Enhancing Cache Architecture Using 7T/14T hybrid SRAM
105	Peak Power Modeling for Data Center Servers with Switched-Mode Power Supplies
106	Diet SODA: A Power-Efficient Processor for Digital Cameras
107	Load-Matching Adaptive Task Scheduling for Energy Efficiency in Energy Harvesting Real-Time Embedded Systems
110	HERQULES: SYSTEM LEVEL CROSS-LAYER DESIGN EXPLORATION FOR EFFICIENT ENERGY-QUALITY TRADE-OFFS
114	In-Situ Power Monitoring scheme and its application in Dynamic Voltage and Threshold Scaling for Digital CMOS integrated circuits
115	Replication-Aware Leakage Management in Chip Multiprocessors with Private L2 Caches
117	Dynamic Indexing: Concurrent Leakage and Aging Optimization for Caches
118	RealEnergy: a New Framework and a Case Study to Evaluate Power-Aware Real-Time Scheduling Algorithms
121	Automatic Synthesis of Near-Threshold Circuits with Fine-Grain Performance Tunability
123	Energy Efficient Proactive Thermal Management in Memory Subsystem
124	Wakeup Synthesis and Its Buffered Tree Construction for Power Gating Circuit Designs
125	Power-performance Management on an IBM POWER7 Server
126	Statistical Leakage Modeling for Accurate Yield Analysis: The CDF Matching Method and Its Alternatives
127	Energy Efficient Implementation of Parallel CMOS Multipliers with Improved Compressors
130	Dynamic Thermal Management for Single and Multicore Processors Under Soft Thermal Constraints
132	Customizing Pattern Set for Test Power Reduction via Improved X-identification and Reordering
137	Low-power Dual-element Memristor-Based Memory Design
138	Low-Power DWT-Based Quasi-Averaging Algorithm and Architecture for Epileptic Seizure Detection
139	Exploring Custom Instruction Synthesis for Application-Specific Instruction Set Processors with Multiple Design Objectives
145	An Energy Efficient Cache Design Using Spin Torque Transfer (STT) RAM.
148	Power-Efficient Variation-Aware Photonic On-Chip Network Management
149	A Pareto-Algebraic Framework for Signal Power Optimization in Global Routing
158	3D-NonFAR: Three-Dimensional Non-Volatile FPGA ARchitecture Using Phase Change Memory
160	A Low-Power Clock Gating Cell Optimized for Low-Voltage Operation in a 45-mn Technology
162	Analysis of Thermal Behaviors of Spin-Torque-Transfer RAM: A Simulation Study
163	Dynamic Workload Characterization for Power Efficient Scheduling on CMP Systems
164	Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing
166	RAPL: Memory Power Estimation and Capping
169	VAIL: Variation-Aware Issue Logic and Performance Binning for Processor Yield and Profit Improvement
170	Low-Power Sub-threshold Design of Secure Physical Unclonable Functions
173	PASAP: Power Aware Structured ASIC Placement
175	Analysis and Design of Ultra Low Power Thermoelectric Energy Harvesting Systems
176	Post-Silicon Power Characterization Using Thermal Infrared Emissions
178	Custom Feedback Control: Enabling Truly Scalable On-Chip Power Management for MPSoCs
179	Dynamic Thermal Management for Networked Embedded Systems under Harsh Ambient Temperature Variation
181	Workload-Aware Neuromorphic Design of Low-Power Supply Voltage Controller
186	A Three-Phase Power-Gating Turn-on Technique for Controlling Ground Bounce Noise
188	Exploiting Power Budgeting in Thermal-Aware Dynamic Placement for Reconfigurable Systems
196	Variation Aware Performance Analysis of Gain Cell Embedded DRAMs
197	Large-Scale Battery System Modeling and Analysis for Emerging Electric-Drive Vehicles
205	PEEC Based Parasitic Modeling for Power Analysis on Custom Rotary Rings
206	Accurate Modeling and Calculation of Delay and Energy Overheads of Dynamic Voltage Scaling in Modern High-Performance Microprocessors