Keynote Speakers
From data centers to mobile devices, the transport of high-speed data continues to present challenges.
The matter of power consumption in wireline transceivers has reached new dimensions, posing two key questions.
First, how does the power scale with speed?
Second, should we be concerned with the power normalized to the bit rate (the "power efficiency") or the absolute power per link?
To address these questions, we naturally seek the lower bounds for the power drawn by each function in the system.
Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on analog and RF integrated circuits. Prof. Razavi has served as an IEEE Distinguished Lecturer and published more than 200 papers and eight books.
He has received nine IEEE best paper awards and six teaching and education awards, and his books have been published in seven languages. He received the IEEE Pederson Award in Solid-State Circuits and was recognized as a top author in
the 50-year and 75-year histories of the IEEE International Solid-State Circuits Conference. He is a member of the US National Academy of Engineering and a fellow of the US National Academy of Inventors.
Behzad Razavi
Professor at University of California, Los Angeles
Abstract
This presentation delves into various building blocks in a wireline environment and quantifies their speed-power tradeoffs,
thus arriving at fundamental bounds. We focus on three sections of the system, namely, the transmitter, the receiver,
and the clock generator, and formulate their performance. The objective is to identify the most power-hungry functions
and explore methods of easing their speed-power trade-offs.
Biography
|
|
Vivek De Intel Fellow and Director of Circuit Technology Research Intel Labs, USA |
Abstract
SoC design challenges and opportunities for smart and secure cyberphysical systems in the world of Internet-of-Things (IoT) are presented, focusing on two distinct areas: (1) how to deliver uncompromising performance and user experience while minimizing energy consumption, and (2) how to provide cryptographic-quality “roots of trust” in silicon and resistance to physical side channel attacks with minimal overhead. SoC designs that span a wide range of performance and power across diverse platforms and workloads, and achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS, are discussed. Techniques to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations are presented. True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) circuits, the two critical silicon building blocks for generating dynamic and static entropy for encryption keys and digital fingerprints, respectively, are discussed. Power and electromagnetic physical side-channel-attack detection and mitigation techniques for enabling robust hardware security are also presented.
Biography
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for leading and inspiring long-term research in future circuit technologies and design techniques for system-on-chip (SoC) designs with focus on energy efficiency. He has 360 publications in refereed international conferences and journals with a citation H-index of 87, and 241 patents issued with 25 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He is the recipient of the 2019 IEEE Circuits and System Society (CASS) Charles A. Desoer Technical Achievement Award for “pioneering contributions to leading-edge performance and energy-efficient microprocessors & many-core system-on-chip (SoC) designs” and the 2020 IEEE Solid-State Circuits Society (SSCS) Industry Impact Award for “seminal impact and distinctive contributions to the field of solid-state circuits and the integrated circuits industry”. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.
|
|
Kyomin Sohn Samsung Master (VP of Technology), DRAM Design Team Samsung Electronics, South Korea |
Abstract
The era of on-device AI is upon us. From GPT applications to the explosive popularity of AI, it is now easy to find around us and is creating reasons to change our smartphones. While cloud computing provides powerful performance, on-device AI research is actively being conducted for privacy and security reasons for personal data, and the development of an on-device AI computing system that is sensitive to energy efficiency and form factor is needed, unlike conventional AI accelerators. Memory companies are preparing various memory solutions for this. These include faster and more efficient LPDDR6 as an extension of existing LPDDR5, LLW DRAM, which can be considered the mobile version of HBM for server application, and DRAM with more innovative PIM technology. In this speech, I will explain various memory solutions and especially PIM technology. Unlike other memories, significant improvements in performance and energy efficiency are possible, but there are also additional considerations to take into account. I will share our perspective on PIM technology from the standpoint of a memory company and its future prospects.
Biography
Kyomin Sohn is a Samsung Master (VP of Technology) in Samsung Electronics and he is responsible for future architecture and circuit technology of DRAM. He received the B.S. and M.S. degrees in Electrical Engineering in 1994 and 1996, respectively, from Yonsei University, Seoul. From 1996 to 2003, he was with Samsung Electronics, Korea, involved in SRAM Design Team. He designed various kinds of high-speed SRAMs. He received the Ph.D. degree in EECS in 2007 from KAIST, Korea. He rejoined Samsung Electronics in 2007, where he has been involved in DRAM Design Team. Especially, He led the developement of HBM2 DRAMs and HBM-PIM. His interests include 3D-DRAM, reliable memory design, and processing-in-memory. In addition, he has currently served as a Technical Program Committee member of Symposium on VLSI Circuits since 2012.