Emerging Technologies and Designs for Low Power 281R Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits 197R Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits 222 Robust Level Converter Design for Subthreshold logic 106 Integrated Solar Energy Harvesting and Storage 145 Power/Energy Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm) Microarchitectural techniques for low power 16R Stall Cycle Redistribution in a Transparent Fetch Pipeline 53R Selective Writeback: Exploiting Transient Values for Energy-Efficiency and Performance 111 Energy-Efficient Dynamic Instruction Scheduling Logic through Instruction Grouping 134 Independent Front-end and Back-end Dynamic Voltage Scaling for a GALS Microarchitecture 29 Synergistic Temperature and Energy Management in GALS Processor Architectures Circuit techniques for scaled technologies 10R A Two-Port SRAM for Real-Time Video Processor Saving 53% of Bitline Power with Majority Logic and Data-Bit Reordering 250R A High-Speed Variation-Tolerant Interconnect Technique for Sub-threshold Circuits Using Capacitive Boosting 139 A Dual VDD Boosted Pulsed Bus Technique for Low Power and Low Leakage Operation 228 Time-Borrowing Multi-Cycle On-Chip Interconnects for Delay Variation Tolerance 277 Pulsed Low-Voltage Swiing Latch for Reduced Power Dissipation in High-Frequency Microprocessors Power management and application specific architectures 257R Temporal vision-guided energy minimization for portable displays 66R Dynamic Current Modelling at the Instruction Level 74 Reducing Idle Mode Power in Software Defined Radio Terminals 120 Power reduction in H.264 encoder through algorithmic and circuits transformation 78 Energy-efficient Motion Estimation using Error-Tolerance Thermal and Energy Aware Design 21R Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power 170 Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers 44 An Efficient Chiplevel Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction 214 A Novel Approach for Variation Aware Power Minimization during Gate Sizing Energy Management for Sensor and Memory Systems 100R Adaptive Duty Cycling for Energy Harvesting Systems 172 Power Reduction of Multiple Disks Using Dynamic Cache Resizing and Speed Control 212 Lifetime Aware Resource Management for Sensor Network Using Distributed Genetic Algorithm 261 Everlast: Long-life, Supercapacitor-operated Wireless Sensor Node Leakage Control and Dynamic Power Optimization 280R A Novel Dynamic Power Cutoff Technique (DPCT) for Active Leakage Reduction in Deep Submicron CMOS Circuits 140R Analysis and Modeling of Subthreshold Leakage of RT-Components under PTV and State Variation 110 Power Optimization In A Repeater-Inserted Interconnect Via Geometric Programming 158 Input-specific Dynamic Power Optimization for VLSI Circuits 274 Two-phase Fine-grain Sleep Transistor Insertion Technique in Leakage Critical Circuits Memory Hierarchy and Caches 75R Register File Caching for Energy Efficiency 71R L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture 276 A Low Power SRAM Architecture Based on Segmented Virtual Grounding 45 Process variation aware cache leakage management 191 Substituting Associative Load Queue with Simple Hash Table in Out-of-Order Microprocessors RF CMOS building blocks 253R A Novel Power Optimization Technique for Ultra-low Power RFICs 115R A CMOS Analog Frontend for a Passive UHF RFID Tag 183R High-Speed Low-Power Frequency Divider with Intrinsic Phase Rotator 50R Low distortion switching power amplifier for hearing instruments Temperature-aware design and microarchitecture 232R An optimal analytical solution for processor speed control with thermal constraints 83R Temperature-aware floorplanning for microarchitecture blocks with IPC-Power Dependence Modeling and Transient Analysis 175 Power Efficiency for Variation-Tolerant Multicore Processors: A Limits Study 118 Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture 251 Dynamic Thermal Management for MPEG-2 Decoding Low Power, Low Voltage Circuits and DC/DC Converters 186 Modeling and Analysis of Leakage Induced Damping Effect in Low Voltage LSIs 177 Efficient Scan-Based BIST Scheme for Low Power Dissipation during testing of VLSI chips 94 Dithering Skip Modulator with a Novel Load Sensor for Ultra-wide-load High-Efficiency DC-DC Converters 154 Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique 203 Robust Multiple-Phase Switched-Capacitor DC-DC Converter With Digital Interleaving Regulation Scheme Low Power Architectures and Systems 107R A Low Power Viterbi Decoder Implementation using Scarce State Transition and Path Pruning Scheme for High Throughput Wireless Applications 95R SmartSaver: Turning Flash Drive into a Disk Energy Saver for Mobile Computers 58 An Energy-Efficient Virtual Memory System with Flash Memory as the Secondary Storage 188 Maximizing the Lifetime of Embedded Systems Powered by fuel Cell-Battery hybrids Posters ======= 149P A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs 252P Variability-Aware Device Optimization under ION and Leakage Current Constraints 34P A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers 223P Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design 86P Thread-Associative Memory for Multicore and Multithreaded Computing 57P Hierarchical Value Cache Encoding for Off-chip Data Bus 244P LOGIC CIRCUITS OPERATING IN SUB-THRESHOLD VOLTAGES 98P Reducing Cache Traffic and Energy with Macro Data Load 22P A Low-Power Active Substrate-Noise Decoupling Circuit with Feedforward Compensation for Mixed-Signal SoCs 230P Power -efficient pulse width modulation DC/DC converters with zero voltage swicthing control 47P Behavioral Modeling of Opamp Gain and Dynamic Effects for Power Optimization of Delta-Sigma Modulators and Pipelined ADCs 92P Low-power fanout optimization by using MTCMOS and multi-Vth techniques 194P Modelling Macromodules for High-Level Dynamic Power Estimation of FPGA-based Digital Designs 275P Considering Process Variations During System-Level Power Analysis 76P A New Strategy for Jointly Optimizing Gate Sizing and Supply Voltage in Ultra-Low Energy Circuits 171P Synchronization-Driven Dynamic Speed Scaling for MPSoCs 269P Power Phase Availability in a Commercial Server Workload 195P Reducing Power through Compiler-Directed Barrier Synchronization Elimination 201P Minimizing Energy Consumption of Banked Memories Using Data Recomputation