Keynote Speakers
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Michaela Blott Senior Fellow, AMD Research Group, Dublin, IrelandA |
Abstract
The hype surrounding AI has reached unprecedented levels, with governments and industries engaged in an arm’s race towards Artificial General Intelligence. As AI permeates every aspect of our lives, from smart sensors and hearing aids to automotive, robotics, and high-energy particle physics, we face a diverse range of challenges that extend far beyond the widely discussed performance scalability and power efficiency. These challenges include demanding requirements such as nanosecond latency, tiny footprints, functional safety, while minimizing power consumption. Overall, a high degree of customization is mandated by the diversity in the wide spectrum of applications. This talk provides insights into the broad emerging spectrum of AI applications and discusses our latest research demonstrating how these challenges, ranging from bag tagging to 6G, can be addressed with a comprehensive portfolio of compute fabrics, agile AI stacks and innovative solutions.
Biography
Dr. Michaela Blott is a Senior Fellow at AMD Research. She heads a team of international scientists driving groundbreaking research into AI, from robotics to computer architectures, model optimizations and green AI. Her journey includes a Ph.D. from Trinity College Dublin and a Master's degree from the University of Kaiserslautern, Germany, and brings over 25+ years of experience in leading-edge AI, computer architecture and advanced FPGA design, in research institutions (ETH Zurich and Bell Labs) and development organizations. She is highly active in the research community as industrial advisor to numerous EU projects and research centres, serves on technical program committees and her contributions to the field were further recognized through multiple Women in Tech Awards.
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Kenichi Okada Institute of Science Tokyo, Japan |
Abstract
Growing demand for energy-efficient and highly integrated systems has highlighted the limitations of traditional custom-designed analog circuits in terms of scalability, portability, and design productivity. A new design methodology based on digital standard cells enables analog circuits to be implemented in a fully synthesizable manner. By utilizing a digital standard cell library, this approach simplifies design complexity, enhances portability, and ensures robust performance across PVT variations. Analog building blocks such as PLLs can be effectively realized through this method. Synthesizable analog circuits also offer significant advantages in power consumption. Unlike analog signal processing, which requires substantial power to maintain high SNR, digital processing achieves greater energy efficiency once signals are digitized. This fundamental difference enables power reductions beyond what is possible with conventional analog implementations. The application of digital optimization techniques to analog design brings new benefits for realizing low-power mixed-signal systems. This presentation highlights the fundamental concepts, implementation examples, and future outlook of this evolving design methodology.
Biography
Kenichi Okada received the B.E., M.E., and Ph.D. degrees in communications and computer engineering from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. From 2000 to 2003, he was a Research Fellow of the Japan Society for the Promotion of Science in Kyoto University. In 2003, he joined Tokyo Institute of Technology as an Assistant Professor, where he is currently a Professor of electrical and electronic engineering in Institute of Science Tokyo. He has authored or co-authored more than 500 journal and conference papers. His current research interests include millimeter-wave and terahertz CMOS wireless transceivers for 20/28/39/60/77/79/100/300GHz for 5G, WiGig, satellite and future wireless systems, digital PLL, synthesizable PLL, atomic clock, and ultra-low-power wireless transceivers for Bluetooth Low-Energy, and sub-GHz applications.
Prof. Okada is a member of the Institute of Electrical and Electronics Engineers (IEEE), the Institute of Electronics, Information and Communication Engineers (IEICE), the Information Processing Society of Japan (IPSJ), and the Japan Society of Applied Physics (JSAP). He was a recipient or co-recipient of the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design Award in 2006 and 2011, the ASP-DAC Special Feature Award in 2011 and Best Design Award in 2014 and 2015, the MEXT Young Scientists’ Prize in 2011, the JSPS Prize in 2014, the Suematsu Yasuharu Award in 2015, the MEXT Prizes for Science and Technology in 2017, the RFIT Best Paper Award in 2017, the IEICE Best Paper Award in 2018, the RFIC Symposium Best Student Paper Award in 2019, the IEICE Achievement Award in 2019, the DOCOMO Mobile Science Award in 2019, the IEEE/ACM ASP-DAC Prolific Author Award in 2020, the Kenjiro Takayanagi Achievement Award in 2020, the KDDI Foundation Award in 2020, the IEEE CICC, Best Paper Award in 2020, the IEEE ISSCC Author-Recognition Award in 2023, and more than 50 other international and domestic awards. He is a Fellow of IEEE. He is/was a member of the technical program committees of IEEE International Solid-State Circuits Conference (ISSCC), VLSI Circuits Symposium, European Solid-State Circuits Conference (ESSCIRC), Radio Frequency Integrated Circuits Symposium (RFIC), Asian Solid-State Circuits Conference (A-SSCC), and he is/was also Guest Editors and an Associate Editor of IEEE Journal of Solid-State Circuits (JSSC), an Associate Editor of IEEE Transactions on Microwave Theory and Techniques (T-MTT), a Distinguished Lecturer and AdCom member of the IEEE Solid-State Circuits Society (SSCS).
Generative Artificial Intelligence (Generative AI), Large Language Models (LLMs), and Machine Learning (ML) are rapidly transforming many aspects of AI hardware accelerators and System-on-Chips (SoCs).
The high computational demands and characteristics of emerging AI/ML workloads are dramatically impacting the architecture, VLSI implementation, and circuit design tradeoffs of hardware accelerators.
Furthermore, as we reach the end of Moore’s law, straightforward technology scaling offers limited opportunities for improved energy efficiency and performance.
Instead, we must rely more on domain-specific architectural features and software/hardware design for AI model inferencing and training.
In this talk, we will provide an overview of NVIDIA’s technology innovations, from circuits to software to the entire datacenter,
needed to enable today’s latest supercomputers for GenAI. Next, we will highlight recent work from NVIDIA Research into energy-efficient deep learning inference acceleration,
including optimized accelerator micro-architectures, SW/HW co-design for low-precision quantization, and LLM compression techniques.
We also highlight recent testchips targeting Transformer neural network inference,
including a recent 5nm deep learning inference accelerator testchip that achieves up to 95.6 TOPS/W and
a low-power accelerator for always-on vision.
Brucek Khailany joined NVIDIA in 2009 and is the Senior Director of the Accelerators and VLSI Research group.
He leads research projects in energy efficient AI accelerators, innovative VLSI design methodologies, ML and GPU assisted EDA,
and quantum computing. Over 15 years at NVIDIA, he has contributed to many projects in research and product groups spanning computer architecture and VLSI design.
Prior to NVIDIA, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc where he led R&D related to parallel processor architectures.
At Stanford University, he led the VLSI implementation of the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations.
He received his PhD in Electrical Engineering from Stanford University and BSE degrees in Electrical and Computer Engineering from the University of Michigan.
Brucek Khailany
Senior Director of the Accelerators and VLSI Research Group, NVIDIA Corporation, USA
Abstract
Biography