Keynote Speakers
Generative Artificial Intelligence (Generative AI), Large Language Models (LLMs), and Machine Learning (ML) are rapidly transforming many aspects of AI hardware accelerators and System-on-Chips (SoCs).
The high computational demands and characteristics of emerging AI/ML workloads are dramatically impacting the architecture, VLSI implementation, and circuit design tradeoffs of hardware accelerators.
Furthermore, as we reach the end of Moore’s law, straightforward technology scaling offers limited opportunities for improved energy efficiency and performance.
Instead, we must rely more on domain-specific architectural features and software/hardware design for AI model inferencing and training.
In this talk, we will provide an overview of NVIDIA’s technology innovations, from circuits to software to the entire datacenter,
needed to enable today’s latest supercomputers for GenAI. Next, we will highlight recent work from NVIDIA Research into energy-efficient deep learning inference acceleration,
including optimized accelerator micro-architectures, SW/HW co-design for low-precision quantization, and LLM compression techniques.
We also highlight recent testchips targeting Transformer neural network inference,
including a recent 5nm deep learning inference accelerator testchip that achieves up to 95.6 TOPS/W and
a low-power accelerator for always-on vision.
Brucek Khailany joined NVIDIA in 2009 and is the Senior Director of the Accelerators and VLSI Research group.
He leads research projects in energy efficient AI accelerators, innovative VLSI design methodologies, ML and GPU assisted EDA,
and quantum computing. Over 15 years at NVIDIA, he has contributed to many projects in research and product groups spanning computer architecture and VLSI design.
Prior to NVIDIA, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc where he led R&D related to parallel processor architectures.
At Stanford University, he led the VLSI implementation of the Imagine processor, which introduced the concepts of stream processing and partitioned register organizations.
He received his PhD in Electrical Engineering from Stanford University and BSE degrees in Electrical and Computer Engineering from the University of Michigan.
Brucek Khailany
Senior Director of the Accelerators and VLSI Research Group, NVIDIA Corporation, USA
Abstract
Biography
|
|
Michaela Blott Senior Fellow, AMD Research Group, Dublin, IrelandA |
Abstract
The hype surrounding AI has reached unprecedented levels, with governments and industries engaged in an arm’s race towards Artificial General Intelligence. As AI permeates every aspect of our lives, from smart sensors and hearing aids to automotive, robotics, and high-energy particle physics, we face a diverse range of challenges that extend far beyond the widely discussed performance scalability and power efficiency. These challenges include demanding requirements such as nanosecond latency, tiny footprints, functional safety, while minimizing power consumption. Overall, a high degree of customization is mandated by the diversity in the wide spectrum of applications. This talk provides insights into the broad emerging spectrum of AI applications and discusses our latest research demonstrating how these challenges, ranging from bag tagging to 6G, can be addressed with a comprehensive portfolio of compute fabrics, agile AI stacks and innovative solutions.
Biography
Dr. Michaela Blott is a Senior Fellow at AMD Research. She heads a team of international scientists driving groundbreaking research into AI, from robotics to computer architectures, model optimizations and green AI. Her journey includes a Ph.D. from Trinity College Dublin and a Master's degree from the University of Kaiserslautern, Germany, and brings over 25+ years of experience in leading-edge AI, computer architecture and advanced FPGA design, in research institutions (ETH Zurich and Bell Labs) and development organizations. She is highly active in the research community as industrial advisor to numerous EU projects and research centres, serves on technical program committees and her contributions to the field were further recognized through multiple Women in Tech Awards.