Final Program
The PDF with the final program can be found HERE.
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08:00 – 08:30 |
Conference Registration |
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08:30 – 09:00 |
Welcome by General and Program Co-Chairs |
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09:00 – 10:00 |
Keynote Talk 1:
Hsien-Hsin Sean Lee, AI Facebook |
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10:00 – 10:30 |
Coffee Break |
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10:30 – 11:45 |
Session 1.1/1.2 .A |
Session 2.1.A |
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12:00 – 13:30 |
Lunch |
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13:30 – 14:45 |
Session 1.1/1.2 .B |
Session 2.2.A |
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14:45 – 15:15 |
Coffee Break |
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15:15 – 16:30 |
Session 1.3.A |
Session 2.3.A |
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16:30 – 17:30 |
Design Contest Short Presentations |
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17:45 – 20:00 |
Industry Reception with Demos and Industry Perspective Posters |
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9:00 – 10:00 Keynote-1 The
Computing Frontiers of Social Network |
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Session
1.1/1.2.A: Low Power Analog Sensing
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10:30 – 10:55 |
A
Pulse-Width Modulated Cochlear Implant Interface Electronics with 513 µW
Power Consumption |
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10:55 – 11:20 |
A
Sound Activity Detector Embedded Low-Power MEMS Microphone Readout Interface
for Speech Recognition |
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11:20 – 11:45 |
A
Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in
Low Power Mode |
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Session
2.1.A: Power Delivery: Generate, Regulate, Infiltrate
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10:30 – 10:55 |
A
Design Framework for Thermal-Aware Power Delivery Network in 3D MPSoCs with
Integrated Flow Cell Arrays |
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10:55 – 11:20 |
Automatic
GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital
SoCs |
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11:20 – 11:45 |
Power
Delivery Resonant Virus: Concept and Application |
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Session
1.1/1.2.B: Clocking and Communication Techniques
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13:30 – 13:55 |
A
Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D
Integration |
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13:55 – 14:20 |
A
Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm
CMOS |
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14:20 – 14:45 |
Robust
Low Power Clock Synchronization for Multi-Die Systems |
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Session
2.2.A: Low-Power Architectures and Frameworks for ML
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13:30 – 13:55 |
An
Automated Approximation Methodology for Arithmetic Circuits |
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13:55 – 14:20 |
An
Ultra-Efficient Memristor-Based DNN Framework with Structured Pruning and
Quantization Using ADMM |
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14:20 – 14:45 |
DYSPINDLE : DYNAMIC SPIKE BUNDLING FOR ENERGY-EFFICIENT SPIKING NEURAL NETWORKS Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani and Anand Raghunathan |
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Session
1.3.A: Low Power On-Chip and Chip-To-Chip Communication
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15:15 – 15:40 |
On
Trade-off Between Static and Dynamic Power Consumption in NoC Power Gating |
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15:40 – 16:05 |
Muffin:
Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers |
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16:05 – 16:30 |
Concurrent
Multipoint-to-Multipoint Communication on Interposer Channels |
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Session
2.3.A: Artificial Intelligence in System Design
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15:15 – 15:40 |
TEA-DNN:
the Quest for Time-Energy-Accuracy Co-optimized Deep Neural Networks |
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15:40 – 16:05 |
CNN-based
Camera-less User Attention Detection for Smartphone Power Management |
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16:05 – 16:30 |
MemGANs:
Memory Management for Energy-Efficient Acceleration of Complex Computations
in Hardware Architectures for Generative Adversarial Networks |
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Industry Perspective Posters (Presented during Industry Reception) |
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1 |
Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology Ricardo Gomez Gomez, Edwige Bano and Sylvain Clerc |
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2 |
Enhanced 3D Implementation of an Arm Cortex-A Microprocessor Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha and Brian Cline |
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Design Contest Demos (Pitch Session and during Industry Reception) |
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Processor Innovations |
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1 |
Exceeding Pessimistic
Margins on ARMv8 Servers for Energy Efficient Processing in Edge/Cloud |
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2 |
Energy-Quality Scalable
Monocular Depth Estimation for Embedded Systems |
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3 |
Implementation of
Software Defined Energy Management for Xilinx Zynq UltraScale+ MPSoC |
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4 |
A 50MHz Low Power SoC
Operating on a 0.48V Supply at 25°C |
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5 |
Design and Validation of
A Two-Phase Gravity-Driven Micro-Scale Thermosyphon |
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6 |
Realizing
Energy-Efficient Dependable Systems with Variably-Reliable DRAMs |
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7 |
An 88fJ / 40 MHz [0.4V]
– 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8x8-bit Multiplier Accumulator with a
Self-Adjustment Mechanism in 28 nm FD-SOI |
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Machine Learning |
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8 |
Efficient Model
Compression and Hardware-Aware Quantization for Object Detection on FPGAs |
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9 |
Thinker-IM: An
Energy-Efficient Speech Recognition Processor with Computing-in-Memory SRAM
and Predictive Execution |
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10 |
Vau da Muntanialas:
Towards Real-Time Speech Recognition on an Energy-Efficient Systolic Array of
LSTM Accelerators |
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11 |
Neuromorphic System for
Temporal Data Classification |
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12 |
An Embedded Deep
Learning Accelerator for Intelligent Microcontroller Units |
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13 |
STICKER: An energy
efficient sparse-aware neural network processor |
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Edge Devices |
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14 |
FLASH: Content-based
Power-saving Design for Scrolling Operations in Browser Applications on
Mobile OLED Devices |
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15 |
Always-On VGA Vision
Sensor with Pixel-Wise Double-Threshold Background Rejection for
Event-Detection |
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2 |
e-Glass for Real-Time
Brain Activity Monitoring in the Internet of Things (IoT) Era |
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17 |
Self-Sustainable
Embedded High-Precision and Low Latency UWB Localization |
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18 |
2.45-GHz Wireless Power
Transfer for BLE-connected Smart Motion Detection Sensor |
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19 |
PULP-DroNet: Open Source
and Open Hardware Artificial Intelligence for Fully Autonomous Navigation on
Nano-UAVs |
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20 |
InfiniWolf: A
Self-Sustaining and Energy Efficient Multi-Sensor SmartWatch |
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21 |
SecureTouch: A
Zero-Power Reciever For Body Communication and Secure Applications |
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09:00 – 10:00 |
Keynote Talk 2: Prof. Luca Benini, ETH Zurich |
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10:00 – 10:30 |
Coffee Break |
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10:30 – 11:45 |
Session 1.1/1.2 .C |
Session 2.2.B |
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12:00 – 13:30 |
Lunch |
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13:30 – 14:45 |
Session 1.3.B Approximation for High Energy and Computational Efficiency |
Session 2.3.B |
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14:45 – 15:15 |
Coffee Break |
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15:15 – 16:30 |
Session 1.3.C |
Special Session |
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18:30 – 22:00 |
Banquet + Awards (Olympic Museum) |
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9:00 – 10:00 Keynote-2 Extreme Edge AI–The Parallel Ultra-low Power (PULP) Approach |
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Session
1.1/1.2.C: Machine Learning Circuits and Memory Design
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10:30 – 10:55 |
K-Nearest
Neighbor Hardware Accelerator Using In-Memory Computing SRAM |
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10:55 – 11:20 |
A
Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of
Deep Neural Networks |
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11:20 – 11:45 |
A
65nm switched source line sub-threshold ROM using data encoding, with 0.3V
Vmin and 47fJ/b access energy |
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Session
2.2.B: Low-power Edge Computing Systems
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10:30 – 10:55 |
Autonomous
I/O for Intermittent IoT Systems |
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10:55 – 11:20 |
BottleNet:
A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services |
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11:20 – 11:45 |
Similarity-Based
LSTM Architecture for Energy-Efficient Edge-Level Speech Recognition |
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Session
1.3.B: Approximation for High Energy and Computational Efficiency
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13:30 – 13:55 |
MixNet:
An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator |
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13:55 – 14:20 |
A²M:
Approximate Algebraic Memory Using Polynomial Rings |
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14:20 – 14:45 |
Compressing
Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware
Acceleration |
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Session
2.3.B: Energy-Efficient Software for Mobile Applications
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13:30 – 13:55 |
FLASH:
Content-based Power-saving Design for Scrolling Operations in Browser
Applications on Mobile OLED Devices |
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13:55 – 14:20 |
Balancing
Memory Accesses for Energy-Efficient Graph Analytics Accelerators |
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14:20 – 14:45 |
Rethinking
Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with
Asymmetric Write Energy |
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Session
1.3.C: Memory Efficiency Improvement
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15:15 – 15:40 |
Improving
Energy Efficiency by Memoizing Data Access Information |
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15:40 – 16:05 |
Exploring
the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling
Efficiency |
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16:05 – 16:30 |
SHRIMP:
Efficient Instruction Delivery with Domain Wall Memory |
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Special
Session: In-Memory Computing
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15:15 – 15:40 |
Unified
Memory-Computing Architecture with Memristive Devices |
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15:40 – 16:05 |
Phase-change memory enables energy-efficient brain-inspired computing Manuel Le Gallo |
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16:05 – 16:30 |
Slashing
energy and runtime with BLADE, an in-cache computing architecture for edge
devices |
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09:00 – 10:00 |
Keynote Talk 3: Prof.
Giovanni De Micheli, EPFL |
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10:00 – 11:00 |
Poster Session |
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11:00 – 12:15 |
Session 1.3/2.3.D |
Session 2.1/2.2/2.3 |
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12:30 – 14:00 |
Lunch |
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9:00 – 10:00 Keynote-3 Nanosystems: Technology and Tools |
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10:00 – 11:00 Poster Session |
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1 |
3DTUBE: A DESIGN FRAMEWORK FOR HIGH-VARIATION CARBON NANOTUBE-BASED TRANSISTOR TECHNOLOGY Aporva Amarnath, Javad Bagherzadeh, Jielun Tan and Ron Dreslinski |
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2 |
A PROBABILISTIC APPROACH TO ENERGY-CONSTRAINED MIXED-CRITICALITY SYSTEMS F. Reghenzani, G. Massari and W. Fornaciari |
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3 |
ADDRESSING TEMPORAL VARIATIONS IN QUBIT QUALITY METRICS FOR PARAMETERIZED QUANTUM CIRCUITS M. ALAM, A. Ash- Saki and S. Ghosh |
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4 |
AN ENERGY EFFICIENT ON-CHIP LEARNING ARCHITECTURE FOR STDP BASED SPARSE CODING H. Kim, H. Tang and J. Park |
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5 |
BATTERY-AWARE ELECTRIC TRUCK DELIVERY ROUTE PLANNER D. Baek, Y. Chen, N. Chang, E. Macii, M. Poncino |
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6 |
COMPHD: EFFICIENT HYPERDIMENSIONAL COMPUTING USING MODEL COMPRESSION J. Morris, M. Imani, S. Bosch, A. Thomas, H. Shu and T. Rosing |
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7 |
FPGA-based Acceleration of Binary
Neural Network Training with Minimized Off-Chip Memory Access |
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8 |
ENERGY-AUTONOMOUS MCU OPERATING IN SUB-VT REGIME WITH TIGHTLY-INTEGRATED ENERGY-HARVESTER J. Deng, J.-L. Nagel, L. Zahnd, M. Pons, D. Ruffieux, C. Arm, P. Persechini and S. Emery |
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LOCAL LEARNING IN RRAM NEURAL NETWORKS WITH SPARSE DIRECT FEEDBACK ALIGNMENT B. Crafton, P. Basnet, M. West, E. Vogel and A. Raychowdhury |
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MESSAGEFUSION: ON-PATH MESSAGE COALESCING FOR ENERGY EFFICIENT AND SCALABLE GRAPH ANALYTICS L. Belayneh, A. Addisie and V. Bertacco |
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MODELING AND OPTIMIZATION OF CHIP COOLING WITH TWO-PHASE VAPOR CHAMBERS Z. Yuan, G. Vaartstra, P. Shukla, S. Reda, E. Wang and A. Coskun |
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12 |
NON-VOLATILE MEMORY UTILIZING RECONFIGURABLE FERROELECTRIC TRANSISTORS TO ENABLE DIFFERENTIAL READ AND ENERGY-EFFICIENT IN-MEMORY COMPUTATION. S. K. Thirumala, S. Jain, A. Raghunathan and S. Gupta |
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13 |
SECO: A SCALABLE ACCURACY APPROXIMATE EXPONENTIAL FUNCTION VIA CROSS-LAYER OPTIMIZATION D. Wu, T. Chen, C.-F. Chen, O. Ahia, J. San Miguel, M. Lipasti and Y. Kim |
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14 |
SHINE: A NOVEL SHA-3 IMPLEMENTATION USING RERAM-BASED IN-MEMORY COMPUTING K. Nagarajan, S. S. Ensan, M. N. I. Khan, S. Ghosh and A. Chattopadhyay |
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15 |
TEMPERATURE-AWARE ADAPTIVE VM ALLOCATION IN HETEROGENEOUS DATA CENTERS Y. G. Kim, J. I. Kim, S. H. Choi, S. Y. Kim and S. W. Chung |
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16 |
TIP: A TEMPERATURE EFFECT INVERSION-AWARE ULTRA-LOW POWER SYSTEM-ON-CHIP PLATFORM K. Han, S. Lee, J.-J. Lee, W. Lee and M. Pedram |
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Session 1.3/2.3.D:
Application-Centric Optimization of Emerging Technologies
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11:00 – 11:25 |
RAPID: A ReRAM
Processing in Memory Architecture for DNA Sequence Alignment |
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11:25 – 11:50 |
HR3AM: a Heat Resilient
design for RRAM based neuromorphic computing |
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11:50 – 12:15 |
NCFET-Aware Voltage
Scaling |
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Session 2.1/2.2/2.3: Optimization Methodologies for Unconventional Digital System Designs |
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11:00 – 11:25 |
Towards a Complete
Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs |
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11:25 – 11:50 |
Tier Partitioning and
Flip-flop Relocation Methods for Clock Trees in Monolithic 3D ICs |
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11:50 – 12:15 |
VCAM: Variation
Compensation through Activation Matching for Analog Binarized Neural Networks |
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