Call for Papers

The International Symposium on Low Power Electronics and Design (ISLPED) is the premier venue for presenting innovative research in all aspects of low power electronics and design, including process technologies, analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, optimization, system software, and applications.

Topics of interest

Specific topics include, but are not limited to, the following three main tracks and sub-areas:

Track 1. Technology, Circuits, and Architecture

1.1. Technologies and Circuits

Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models. Low-power circuits for logic, memory, reliability, yield, clocking, resiliency; low-power analog/mixed-signal circuits for wireless, RF, MEMS, ADC/DAC, I/O, PLLs/DLLs, DC-DC converters; energy-efficient circuits for emerging applications (e.g., neuromorphic, biomedical, in-vitro sensing, autonomous); circuits using emerging technologies; cryogenic circuits. DTCO for low power; combinatorial optimizers (Ising machine). AI/ML-based circuit optimization; circuit architecture for power-efficient AI applications.

1.2. Logic and Architecture

Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power. AI/ML-assisted logic optimization and architecture exploration. Power efficient architecture for AI.

Track 2. EDA, Systems, and Software

2.1. CAD Tools and Methodologies

CAD tools, methodologies, and AI/ML-based approaches for low power and thermal-aware design (analog/digital). AI/ML for acceleration of IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm.

2.2. Systems and Platforms

Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design.

2.3. Software and Applications

Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW co-design, and emerging low-power AI/ML applications.

2.4. Hardware and System Security

Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; confidential computing; energy-efficient approaches to system security.

Track 3. AI/ML, Quantum and Emerging Hardware

3.1. Analog, Mixed-Signal & Emerging AI Hardware

Analog and mixed-signal computing architectures for AI/ML including analog matrix multiplication, in-memory computing, and compute-in-memory techniques; emerging device technologies such as memristors, ReRAM, phase-change memory, and photonic computing; neuromorphic and brain-inspired computing systems including spiking neural networks; circuit design techniques for analog AI accelerators including ADC/DAC design, switched-capacitor networks, and noise-resilient architectures; EDA tools and methodologies for analog/mixed-signal AI systems including simulation, verification, and layout automation; process variation mitigation and robustness techniques for non-ideal analog computation.

3.2. Digital AI Hardware & Systems

Digital accelerator architectures including systolic arrays, dataflow architectures, and tensor processing units; ASIC, FPGA, and GPU-based implementations for AI/ML workloads; memory hierarchy design and optimization including high-bandwidth memory, scratchpads, and cache architectures; sparse computation and quantization hardware; RTL design, verification, and synthesis for AI accelerators; logic synthesis, place-and-route, timing closure, and power optimization for ML chips; system-level design including network-on-chip, interconnects, and multi-chip systems; compiler, runtime, and systems software for AI hardware; performance modeling, simulation, and design space exploration tools.

3.3. Quantum Computing and Emerging Computing Technologies

Quantum computing hardware platforms including superconducting qubits, trapped ions, and photonic systems; quantum algorithms, error correction, and fault tolerance; quantum circuit compilation and optimization; NISQ algorithms and hybrid quantum-classical systems; emerging post-CMOS paradigms including DNA computing, molecular computing, photonic computing, and probabilistic computing; neuromorphic and spin-based computing; EDA tools, programming frameworks, and benchmarking methodologies for quantum and emerging computing platforms.

Track 4. Industrial Design Track

Industrial Design Track

This track solicits papers to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs.

Submission

Papers are submitted electronically through the ISLPED 2026 submission system.

Length Up to 6 pages, double-column, plus 1 additional page for references only
Format ACM Conference proceedings template, US Letter size
Review Double-blind — submissions must be anonymous

Submit a paper → ACM template Full CfP (PDF)

Conflict-of-Interest Definitions

The conference defines conflicts of interest between reviewers and authors as follows:

Advisor–advisee relationships — between advisor and advisee, forever.
Family connections — between family members, forever.
Recent collaboration — between people who have collaborated in the last 4 years. This encompasses joint research, co-authored papers, or direct personal funding arrangements. Professional activities such as tutorials do not constitute conflicts.
Institutional affiliation — between people from the same institution, or who were at the same institution in the last 4 years.
Objectivity concerns — between people whose relationship prevents the reviewer from being objective in their assessment.

When there is uncertainty about whether a relationship constitutes a conflict, authors should consult the program committee chairs for clarification.