ISLPED 2026

Keynotes

Three keynotes across the three-day program, spanning in-memory computing, nonlinear silicon, and near-data architectures for energy-efficient AI.

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  Day 1 · Wednesday, August 5

  Naveen Verma

  Ralph H. and Freda I. Augustine Professor of Electrical and Computer Engineering · Co-Founder & CEO of EnCharge AI

  Princeton University · EnCharge AI

  In-Memory Computing for Next-Generation AI: low-power design applied to a new era of circuits and architectures

  Most deployments of AI will be power limited, because its usefulness is driving more AI across platforms, from the Edge to the Data Center. The efficiency gap is so acute, that transformative circuits and architectures will be required. This, in turn, drives a critical evolution in how we think about low-power systems design. This talk focuses on the approach of in-memory computing (IMC), which has gained a high level of interest, due to its ability to solve the two-sided problem of arithmetic efficiency and data-movement. This talk surveys the major findings and lessons learned as the industry moves towards this transformative technology, particularly based on analog operation. The insights start at the level of fundamental tradeoffs, and drive essential implications at the device, circuit, architectural, and algorithmic levels. Specifically focusing on practical architectures for delivering scaled-up system-level efficiency inflections brings to the forefront critical challenges for many analog pathways, while illuminating approaches that can and are driving large efficiency boosts, as prevailing digital trajectories are saturating. As we think about these, it is also essential to consider how such inflections can be constructively adopted in increasingly complex and multi-faceted ecosystem and system requirements, and not break the way systems are constructed today and in the future. This requires considering architectural and software design approaches, as well as alignments with key industrial trends.

  Biography. Naveen Verma received the B.A.Sc. degree in Electrical and Computer Engineering from the UBC, Vancouver, Canada in 2003, and the M.S. and Ph.D. degrees in Electrical Engineering from MIT in 2005 and 2009 respectively. Since July 2009 he has been at Princeton University, where he is currently the Ralph H. and Freda I. Augustine Professor of Electrical and Computer Engineering. His research focuses on advanced sensing and computing systems. This includes research on large-area flexible sensors, energy-efficient computing architectures and circuits, and machine-learning and statistical-signal-processing algorithms. Prof. Verma has been involved in a number of technology transfer activities including founding start-up companies. Most recently, he co-founded EnCharge AI, together with industry leaders in AI computing systems, to commercialize foundational technology developed in his lab. Prof. Verma has served as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, and on a number of conference program committees and advisory groups. Prof. Verma is the recipient of numerous teaching and research awards, including several best-paper awards, with his students.

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  Day 2 · Thursday, August 6

  Wilfred G. van der Wiel

  Professor of Nanoelectronics · Co-Director, BRAINS Center for Brain-Inspired Computing

  University of Twente · University of Münster

  Reconfigurable Nonlinear Computing in Silicon

  Most AI hardware accelerates linear operations, in particular matrix-vector multiplications. However, neural networks derive much of their expressive power from nonlinear transformations. This motivates hardware that performs nonlinear processing directly in physical devices. In this talk, I will discuss reconfigurable nonlinear-processing units (RNPUs): silicon-based, multi-terminal nanoelectronic devices with tunable nonlinear input-output characteristics. By exploiting device physics for computation, RNPUs can perform analogue nonlinear transformations locally, reducing data movement, circuit overhead and power consumption. I will highlight recent results on RNPUs, including analogue speech recognition, physical Kolmogorov-Arnold Networks, and the space-charge mechanism underlying the strong nonlinear response. Together, these results point toward a CMOS-compatible route to compact, low-latency and energy-efficient AI hardware.

  Biography. Wilfred G. van der Wiel (Gouda, 1975) is full professor of Nanoelectronics, co-director of the BRAINS Center for Brain-Inspired Computing, and co-chair of the Department of Electrical Engineering at the University of Twente, The Netherlands. He holds a second professorship at the Institute of Physics, University of Münster, Germany. His research focuses on unconventional electronics for efficient information processing. Van der Wiel is a pioneer in material learning at the nanoscale and in the development of reconfigurable nonlinear-processing units (RNPUs), realizing computational functionality directly in nanomaterial substrates through principles analogous to machine learning. He has authored more than 125 journal articles, receiving over 15,000 citations.

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  Day 3 · Friday, August 7

  Hoshik Kim

  Senior Vice President and Fellow, Memory Systems Research

  SK hynix Inc.

  Near-Data Computing: The Energy Imperative

  As AI scales, both industry and academia have long pursued near-data processing as a path to major performance gains. Today, performance is no longer the only challenge—energy is the real bottleneck. Data movement now consumes orders of magnitude more energy than computation itself, making traditional architectures increasingly unsustainable for next-generation AI data centers as well as battery-constrained edge devices. In this new energy-limited computing era, near-data processing has moved from an intriguing idea to a practical necessity. Approaches span in-sensor, in-memory, in-storage, and in-network processing, depending on where data is created and resides. Among them, near-memory processing is rapidly becoming reality. This talk explores the shift toward tightly integrated compute-memory systems, including 3D architectures that dramatically cut data movement and energy use. I expect we will see more domain-specific architectures and heterogeneous systems built around that idea. It's really a move toward a memory-centric design for AI infrastructure.

  Biography. Hoshik Kim is Senior Vice President and Fellow at Memory Systems Research, SK hynix Inc., where he leads research and pathfinding in memory systems architecture and software solution for data centers at scale as well as edge devices. His current research interests focus on next-generation memory systems for AI and HPC, which include memory expansion, tiering, pooling and sharing as well as computational memory/storage solutions such as PIM/PNM, custom HBM, etc. He is also interested in advanced packaging and emerging interconnect technologies for better compute and memory integration. Prior to joining SK hynix, he worked for Intel and LG Electronics, where he gained broad experiences in architecture, design, verification and electronic design automation (EDA) for microprocessors, SoC's and IP's. Hoshik received B.S. from Yonsei University, Seoul, Korea and M.S. and Ph.D. from University of Southern California, all in Electrical Engineering. He is also serving on the Board of Directors for Semiconductor Research Corporation (SRC). Contact him at hoshik.kim@sk.com.